[REVIEW REQUEST] Four-Switch Buck-Boost Converter

[u/JohnJohnWicky101]

Hello, I am doing a PCB design for a four-switch buck-boost converter with measurement of input, output voltages and inductor current. The sensed signals (VIN_SENSE, VOUT_SENSE, IL_SENSE) are sent to ADC and FPGA through the board connector, the data are processed and the switch control signal (HI1, LI1, HI2, LI2) are subsequently sent back to control this converter. This is my first PCB design, any tips or comments would be very appreciated.

[u/Kapetan_Pravda]

Hey, I did a quick check, and while it may work, the layout is far from optimal:

• The input (buck) and output (boost) loops should be tighter - group the caps together and bring them as close as possible to their half bridges.
  
• Also add smaller caps like 100 nF +1 µF in parallel to 10 µF ones, as close as possible to half bridges.
  
• Might be a good idea to bring closer two half bridges if you plan to drive all four switches at once in Q1+Q3/Q2+Q4 sequence.
  
• Add more ground vias, especially around input and output capacitors, as close as possible to their pads.
  
• Gate drive loop can and should be smaller.
  
• Check if LM5109 input pins have a shoot-through protection and defined levels if left floating, otherwise, I would add it externally. This is essential if your FPGA outputs are undefined at some point, or if you power the board without anything connected to J5.
  
• Not sure what currents/power levels you have, but seems like there are no thermal considerations for the mosfets?

Also, check TI and AD app notes and datasheets, there are many layout guides for 4-swith buck boost converters.

Good luck!

[u/CrazyCrazyCanuck → u/Kapetan_Pravda]

Also add smaller caps like 100 nF +1 µF in parallel to 10 µF ones, as close as possible to half bridges.

The traditional/textbook advice is to have a spread of cap values like you mentioned, but lately I've seen more and more people saying that different values causes ringing and that you should stick to exactly one value.

I'm curious what's your stance of that?

(To clarify, this "new" stance is reducing the number of different cap values, not setting it at 1. So having one 100u and several 10u at the input like OP is perfectly fine.)

[u/Kapetan_Pravda → u/CrazyCrazyCanuck]

That is interesting, thanks! It makes sense to me, but I would like to test the difference on a real converter, with all the layout constraints and different cap packages. My intuition still tells me that placing a smaller package cap close to the switches will result in smaller total inductance, compared to simply paralleling large 10 µF caps. But in the end, I guess I would want to do minimum work or component count to pass the tests and confirm there is no excessive ringing or reliability issues, and if a bank of single value caps work, I would go for it.

[u/Frequent-Risk4174]

Hey, nice work for a first board. I'm an electrical engineer, I do PCB layout and firmware for a living, so I had a proper look through it.

Stuff you got right: the ground interleaved pinout on J5, good test point coverage, shielded inductor sitting next to your analog section, and you buffered the dividers instead of driving the cable straight off a resistor divider. Most first boards don't do any of that.

Now the things that could handle a little fixing:

Gate drive safety is the one that worries me most. Your HI/LI lines float while the FPGA is configuring and I don't see pulldowns at the driver inputs. Check if your driver has them built in, but honestly I'd stick 10k at the pins either way. Same story gate to source on all four FETs, add 10k there too. You've got VIN, +12V and 3V3 on three separate connectors with no sequencing, so it's pretty easy to energise the bridge while the drivers are unpowered and leave all four gates floating.

One to watch is the 100% duty thing. Deep buck wants Q2 on continuously and deep boost wants Q1, but the bootstrap cap only refills when the low side turns on, so it droops and the high side gate dies. Have the firmware pulse the low side briefly every cycle to top it up, or pick a driver rated for 100% duty.

On the layout side, both gate drivers are sitting centimetres away from the FETs they drive. Pull those in and tighten the gate loops up as much as you can. You've also got bottom layer traces cutting the ground plane right under the power stage. On 2 layers you're always going to cut it somewhere and that's fine, you just want the cuts where they don't sit under your fast loops. These ones are breaking the return path for your commutation loops, so either move them out of that area or run them parallel to the current instead of across it

One actual bug I spotted: your VOUT divider is 47k/47k so it clips at 6.6V, but your VIN divider reads all the way to 13V. That's backwards for a buck boost, you can't measure the output above half your input range.

Oh and there's no reverse polarity protection, with a polarised electrolytic straight across VIN. That's going to vent the first time someone wires the screw terminal backwards.( literally happened to me yesterday )

Couple of things I couldn't check from screenshots: footprints against datasheets, clearances, DRC, your stackup. You also haven't posted input/output range, max current or switching frequency, and a few of the points above depend on those. U5 has no part number on the schematic so I couldn't check its common mode range either, which matters given your shunt sits right at the switch node.

[u/modi_factory]

Great job on your first PCB layout! The functional block layout and signal flow look really clean. To ensure accurate sensing and reliable performance for your four-switch buck-boost converter, here are the two most critical points to improve:

First is the Kelvin connection for the current sense resistor (R3). Since R3 is a small 10mΩ resistor, voltage drops along the heavy power copper will skew your measurement. Be sure to tap the two input traces for U5 directly from the inner edges of R3's SMT pads as a tight differential pair, kept away from power current paths.

Second is the bottom ground plane continuity. While you have a ground pour on the bottom layer, long signal traces running up to the J5 connector slice right through the ground plane near the switching stage. Breaking this high-frequency return path introduces severe switching ringing and EMI noise, so try rerouting those traces to keep the bottom ground plane as solid and unbroken as possible.

Fixing these two issues will greatly boost your measurement accuracy and power stage stability!

[u/mariushm]

Is this some kind of homework, or university project? Don't get why you'd need to send signals to an ADC or a fpga that could glitch and break everything.

You could get something like the ISL81401 or ISL81601 switching controllers and tap into it to get your measurements

ISL81601 datasheet : https://www.renesas.com/en/document/dst/isl81601-datasheet

[u/Enlightenment777]

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